 
module top(
  input clk_50M,
  input reset,
  output [4:0] led,
  
  output D26,//uart out
 
//  5V
//GND
output C26,
output F24,
input  F27,
input  H21,
input  E26,
input  J24,
input  K27,
input  K22,

output                   mem_odt,
output                   mem_cs_n,
output                   mem_cke,
output           [13:0]  mem_addr,
output           [2:0]   mem_ba,
output                   mem_ras_n,
output                   mem_cas_n,
output                   mem_we_n,
output           [3:0]   mem_dm,
inout                    mem_clk,
inout                    mem_clk_n,
inout           [31:0]   mem_dq,
inout           [3:0]    mem_dqs,

input        USB3_UART_IN,
output       USB3_RST_OUT,
output       USB3_PCLK,
inout [31:0] USB3_DQ,
output [1:0] USB3_A,
output       USB3_SLCS_N,
output       USB3_SLWR_N,
output       USB3_SLOE_N,
output       USB3_SLRD_N,
output       USB3_PKTEND_N,
input        USB3_FLAGA,
input        USB3_FLAGB,
input        USB3_FLAGC,
input        USB3_FLAGD,
input        USB3_CMD_CLK,
input        USB3_CMD_DAT_U2F,
output       USB3_CMD_DAT_F2U,


  input dummy
);


assign D26 = USB3_UART_IN;


reg sys_rst_n ;// && locked_sdram && locked_cpu && locked_vga;
reg [20:0] reset_delay;
always @(posedge clk_50M or negedge reset) begin
  if (!reset) begin
    reset_delay <= 0;
     sys_rst_n <= 0;
  end else begin
    reset_delay <= reset_delay+1'b1;
     if(reset_delay[20])begin
        sys_rst_n <= 1;
     end
  end
end


assign led[0] = flg;
assign led[1] = 1;
assign led[2] = 1;
assign led[3] = 1;
assign led[4] = 1;

reg [31:0] cnt;
reg flg;
always @(posedge clk_50M or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    cnt <= 0;
    flg <= 1;
  end else begin
    cnt <= cnt+1'b1;
     if(cnt==32'd50000000)begin
        cnt <= 0;
        flg <= ~flg;
     end
  end
end










wire ddr2_clk;

wire [31:0] debug_address_out;
wire [31:0] ddr2_addr_out;

reg  [25:0] local_address;
wire [7:0] local_be;
wire local_init_done;

assign local_be = 8'b11111111;

wire [127:0] recorderData;


  wire             ctl_clk;
  wire    [ 13: 0] afi_addr;
  wire    [  2: 0] afi_ba;
  wire             afi_cas_n;
  wire             afi_ras_n;
  wire             afi_cs_n;
  wire             afi_we_n;
  wire             afi_rst_n;

  wire             afi_cke;
  wire             afi_ctl_long_idle;
  wire             afi_ctl_refresh_done;

  wire             afi_odt;
  wire    [ 63: 0] afi_rdata;
  wire    [  3: 0] afi_rdata_en;
  wire    [  3: 0] afi_rdata_en_full;
  wire             afi_rdata_valid;
  wire    [  3: 0] afi_cal_byte_lane_sel_n;
  wire             afi_cal_fail;
  wire             afi_cal_req;
  wire             afi_cal_success;
  wire             afi_mem_clk_disable;
  wire    [  4: 0] afi_rlat;

  wire             ctl_reset_n;
  assign ddr2_clk = ctl_clk;




wire                                                                   wr_data_mem_full;
    assign local_init_done = afi_cal_success;


localparam CFG_MEM_IF_CS_WIDTH = 1;
localparam CFG_AFI_INTF_PHASE_NUM = 2;
localparam CFG_MEM_IF_BA_WIDTH = 3;
localparam CFG_MEM_IF_ROW_WIDTH = 14;
localparam CFG_MEM_IF_COL_WIDTH = 10;
localparam CFG_INT_SIZE_WIDTH = 4;

wire [CFG_MEM_IF_CS_WIDTH    - 1 : 0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH    - 1 : 0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH   - 1 : 0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH   - 1 : 0] cmd_gen_col;

wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CS_WIDTH)  - 1 : 0] bg_to_chipsel;
wire [(CFG_AFI_INTF_PHASE_NUM                  )      - 1 : 0] bg_to_chip;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_BA_WIDTH)  - 1 : 0] bg_to_bank;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_ROW_WIDTH) - 1 : 0] bg_to_row;
wire [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_COL_WIDTH) - 1 : 0] bg_to_col;

assign bg_to_chipsel = 0;
assign bg_to_chip = {1'b1,1'b1};
assign bg_to_bank = {cmd_gen_bank, cmd_gen_bank};
assign bg_to_row = {cmd_gen_row, cmd_gen_row};
assign bg_to_col = {cmd_gen_col, cmd_gen_col};

wire seq_wdp_ovride;
    alt_mem_ddrx_addr_cmd_wrap #
    (
        .CFG_MEM_IF_CKE_WIDTH           (1           ),
        .CFG_MEM_IF_ADDR_WIDTH          (14       ),
        .CFG_MEM_IF_ROW_WIDTH           (CFG_MEM_IF_ROW_WIDTH           ),
        .CFG_MEM_IF_COL_WIDTH           (CFG_MEM_IF_COL_WIDTH           ),
        .CFG_MEM_IF_BA_WIDTH            (CFG_MEM_IF_BA_WIDTH            ),
        .CFG_DWIDTH_RATIO               (2               ),
        .CFG_ODT_ENABLED                (1                ),
        .CFG_MEM_IF_ODT_WIDTH           (1           ),
        .CFG_AFI_INTF_PHASE_NUM         (CFG_AFI_INTF_PHASE_NUM         ),
        .CFG_LOCAL_ID_WIDTH             (8             ),
        .CFG_DATA_ID_WIDTH              (8              ),
        .CFG_INT_SIZE_WIDTH             (4             ),
        .CFG_PORT_WIDTH_TYPE            (3            ),
        .CFG_PORT_WIDTH_CAS_WR_LAT      (4      ),
        .CFG_PORT_WIDTH_TCL             (4             ),
        .CFG_PORT_WIDTH_ADD_LAT         (4         ),
        .CFG_PORT_WIDTH_WRITE_ODT_CHIP  (1  ),
        .CFG_PORT_WIDTH_READ_ODT_CHIP   (1   ),
        .CFG_PORT_WIDTH_OUTPUT_REGD     (2     )
    )
    addr_cmd_wrap_inst
    (
        .ctl_clk                        (ctl_clk                        ),
        .ctl_reset_n                    (ctl_reset_n                    ),
        .ctl_cal_success                (afi_cal_success                ),
        .cfg_type                       ('b001                       ),
        .cfg_tcl                        (5                        ),
        .cfg_add_lat                    (0                    ),
        .cfg_write_odt_chip             (1             ),
        .cfg_read_odt_chip              (0              ),
        .cfg_burst_length               ('b00100               ),
        //.cfg_output_regd_for_afi_output (0 ),
        .bg_do_write                    ({my_do_write, 1'b0}                    ),      
        .bg_do_read                     ({my_do_read, 1'b0}                     ),      
        .bg_do_auto_precharge           ({my_do_auto_precharge, 1'b0}           ),      
        .bg_do_activate                 ({1'b0, my_do_activate}                 ),      
        .bg_do_refresh                  ({do_refresh, do_refresh}       ),      
        .bg_to_chip                     (bg_to_chip                     ),      
        .bg_to_bank                     (bg_to_bank                     ),      
        .bg_to_row                      (bg_to_row                      ),      
        .bg_to_col                      (bg_to_col                      ),      
        .afi_cke                        (afi_cke                        ),
        .afi_cs_n                       (afi_cs_n                       ),
        .afi_ras_n                      (afi_ras_n                      ),
        .afi_cas_n                      (afi_cas_n                      ),
        .afi_we_n                       (afi_we_n                       ),
        .afi_ba                         (afi_ba                         ),
        .afi_addr                       (afi_addr                       ),
        .afi_rst_n                      (afi_rst_n                      ),
        .afi_odt                        (afi_odt                        )
    );
    






wire [63:0] dio_rdata_2xa;

	ddr2_phy_alt_mem_phy	ddr2_phy_alt_mem_phy_inst(
		.pll_ref_clk(clk_50M),
		.global_reset_n(sys_rst_n),
		.soft_reset_n(sys_rst_n),

    .reset_request_n(),

		.ctl_clk(ctl_clk),
		.ctl_reset_n(ctl_reset_n),

		.ctl_dm         (afi_dm),
		.ctl_dqs_burst  (afi_dqs_burst),
		.ctl_wdata      (afi_wdata),
		.ctl_wdata_valid(afi_wdata_valid),

    .dio_rdata_2xa(dio_rdata_2xa),


		.ctl_addr(afi_addr),
		.ctl_ba(afi_ba),
		.ctl_cas_n(afi_cas_n),
		.ctl_cke(afi_cke),
		.ctl_cs_n(afi_cs_n),
		.ctl_odt(afi_odt),
		.ctl_ras_n(afi_ras_n),
		.ctl_we_n(afi_we_n),
		.ctl_rst_n(afi_rst_n),
		.ctl_mem_clk_disable(afi_mem_clk_disable),

		.ctl_doing_rd(afi_rdata_en),
		.ctl_rdata_valid(afi_rdata_valid),
		//.ctl_rlat(afi_rlat),

		.ctl_cal_req(afi_cal_req),
		.ctl_cal_byte_lane_sel_n(afi_cal_byte_lane_sel_n),
		.ctl_cal_success(afi_cal_success),
		.ctl_cal_fail(afi_cal_fail),
		.ctl_cal_warning(),


		.dbg_rd_data(),
		.seq_wdp_ovride(seq_wdp_ovride),

		.mem_addr(mem_addr),
		.mem_ba(mem_ba),
		.mem_cas_n(mem_cas_n),
		.mem_cke(mem_cke),
		.mem_cs_n(mem_cs_n),
		.mem_dm(mem_dm),
		.mem_odt(mem_odt),
		.mem_ras_n(mem_ras_n),
		.mem_we_n(mem_we_n),
		.mem_reset_n(mem_reset_n),
		.mem_clk(mem_clk),
		.mem_clk_n(mem_clk_n),
		.mem_dq(mem_dq),
		.mem_dqs(mem_dqs),
		.mem_dqs_n(mem_dqs_n));

	defparam
		ddr2_phy_alt_mem_phy_inst.FAMILY = "Cyclone IV E",
		ddr2_phy_alt_mem_phy_inst.MEM_IF_MEMTYPE = "DDR2",
		ddr2_phy_alt_mem_phy_inst.DLL_DELAY_BUFFER_MODE = "LOW",
		ddr2_phy_alt_mem_phy_inst.DLL_DELAY_CHAIN_LENGTH = 12,
		ddr2_phy_alt_mem_phy_inst.DQS_DELAY_CTL_WIDTH = 6,
		ddr2_phy_alt_mem_phy_inst.DQS_OUT_MODE = "DELAY_CHAIN2",
		ddr2_phy_alt_mem_phy_inst.DQS_PHASE = 6000,
		ddr2_phy_alt_mem_phy_inst.DQS_PHASE_SETTING = 2,
		ddr2_phy_alt_mem_phy_inst.DWIDTH_RATIO = 2,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DWIDTH = 32,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_ADDR_WIDTH = 14,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_BANKADDR_WIDTH = 3,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_CS_WIDTH = 1,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_CS_PER_RANK = 1,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DM_WIDTH = 4,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DM_PINS_EN = 1,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DQ_PER_DQS = 8,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DQS_WIDTH = 4,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_OCT_EN = 0,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_CLK_PAIR_COUNT = 1,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_CLK_PS = 8000,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_CLK_PS_STR = "8000 ps",
		ddr2_phy_alt_mem_phy_inst.MEM_IF_MR_0 = 594,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_MR_1 = 1092,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_MR_2 = 0,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_MR_3 = 0,
		ddr2_phy_alt_mem_phy_inst.PLL_STEPS_PER_CYCLE = 80,
		ddr2_phy_alt_mem_phy_inst.SCAN_CLK_DIVIDE_BY = 2,
		ddr2_phy_alt_mem_phy_inst.MEM_IF_DQSN_EN = 0,
		ddr2_phy_alt_mem_phy_inst.DLL_EXPORT_IMPORT = "EXPORT",
		ddr2_phy_alt_mem_phy_inst.MEM_IF_ADDR_CMD_PHASE = 90,
		ddr2_phy_alt_mem_phy_inst.DO_CALIB = 1,
		ddr2_phy_alt_mem_phy_inst.RANK_HAS_ADDR_SWAP = 0;



assign cmd_gen_chipsel   = 0;
assign cmd_gen_bank = local_address[CFG_MEM_IF_BA_WIDTH - 1 - 1 + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH : CFG_MEM_IF_ROW_WIDTH - 1 + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_row  = my_do_activate ? local_address[CFG_MEM_IF_ROW_WIDTH - 1 - 1 + CFG_MEM_IF_COL_WIDTH : CFG_MEM_IF_COL_WIDTH - 1] : 0;
assign cmd_gen_col  = coladdr;

//localparam T1 = 1;//数据1
//localparam T2 = 5;//数据2

//1 trans = 16byte
//localparam TRANS_COUNT          = 2;//32 byte
//localparam TRANS_ADDR_WIDTH     = 1;
//localparam TRANS_COUNT          = 4;//64 byte
//localparam TRANS_ADDR_WIDTH     = 2;
//localparam TRANS_COUNT          = 8;//128 byte
//localparam TRANS_ADDR_WIDTH     = 3;
//localparam TRANS_COUNT          = 16;//256 byte
//localparam TRANS_ADDR_WIDTH     = 4;
localparam TRANS_COUNT          = 32;//512 byte
localparam TRANS_ADDR_WIDTH     = 5;
//localparam TRANS_COUNT          = 64;//1024 byte
//localparam TRANS_ADDR_WIDTH     = 6;

localparam DDR2_IDLE          = 0;
localparam DDR2_ACTIVE        = 1;
localparam DDR2_ACTIVE_WAIT   = 2;
localparam DDR2_A             = 3;
localparam DDR2_B             = 4;
localparam DDR2_C             = 5;
localparam DDR2_D             = 6;
localparam DDR2_E             = 7;
localparam DDR2_F             = 8;
localparam DDR2_G             = 9;
localparam DDR2_REFRESH       = 10;
localparam DDR2_FINAL         = 15;

reg [CFG_MEM_IF_COL_WIDTH   - 1 : 0] coladdr;
reg my_do_activate;
reg my_do_write;
reg my_do_read;
reg my_do_auto_precharge;

reg local_rdata_valid;



reg  [  7: 0] afi_dm;
reg  [  3: 0] afi_dqs_burst;
reg  [ 63: 0] afi_wdata;// = local_wdata;
reg  [  3: 0] afi_wdata_valid;

reg [31:0] local_rdata;
reg [63:0] local_rdata0;
reg [63:0] local_rdata1;
wire [63:0] local_wdata;
reg [31:0] local_wdata0;
reg [31:0] local_wdata1;
reg [31:0] local_wdata2;
reg [31:0] local_wdata3;


wire ddr2_req;
wire ddr2_write;
reg  ddr2_ack;

reg ddr2_req_buff;
reg [3:0] status;
reg debug_flg;
reg [TRANS_ADDR_WIDTH+2-1:0] ddr2_addr;
reg resetIndex_buff;
reg [11:0] refresh_cnt;
reg refresh_cntdown_finish1;
reg refresh_cntdown_finish2;
reg refresh_req;
reg refresh_ack;
reg do_refresh;

reg [2:0] ddr2_dly;
reg [3:0] ddr2_timer;
reg [3:0] refresh_cntdown;
reg [TRANS_ADDR_WIDTH-1:0] ddr2_trans_count;
reg [TRANS_ADDR_WIDTH-1:0] trans_count;
reg trans_enable;
reg addr_enable;
reg [1:0] trans_status;
always @(posedge ddr2_clk or negedge reset) begin
  if (!reset) begin
    ddr2_req_buff <= 0;
    status <= 0;
    local_address <= 0;
    debug_flg <= 0;
    ddr2_addr <= 0;
    ddr2_ack <= 0;
    refresh_cnt <= 0;
    refresh_req <= 0;
    refresh_ack <= 0;
    refresh_cntdown <= 0;
    refresh_cntdown_finish1 <= 0;
    refresh_cntdown_finish2 <= 0;
    do_refresh <= 0;

    ddr2_timer <= 0;

    my_do_activate <= 0;
    my_do_read <= 0;
    my_do_write <= 0;
    my_do_auto_precharge <= 0;
    coladdr <= 0;
    ddr2_trans_count <= 0;
    trans_count <= 0;
    trans_enable <= 0;
    addr_enable <= 0;
    trans_status <= 0;
    local_rdata_valid <= 0;
    ddr2_dly <= 0;
    local_rdata <= 0;
    local_rdata0 <= 0;
    local_rdata1 <= 0;
    afi_dm <= 8'b11111111;
    afi_dqs_burst <= 4'b0000;
    afi_wdata <= 0;
    afi_wdata_valid <= 4'b0000;
  end else begin
    ddr2_req_buff <= ddr2_req;

    if(refresh_cnt==4095)begin//975
      refresh_req <= 1;
    end else begin
      if(local_init_done)begin
        refresh_cnt <= refresh_cnt + 1'b1;
      end
    end

    if(refresh_ack)begin
      refresh_req <= 0;
      refresh_cnt <= 0;
    end

    refresh_cntdown_finish1 <= refresh_cntdown==3;//7.5ns
    refresh_cntdown_finish2 <= refresh_cntdown==15;//195ns
         
    
    refresh_ack <= 0;
    do_refresh <= 0;
    
    afi_dm <= 8'b11111111;
    afi_dqs_burst <= 4'b0000;
    afi_wdata <= 0;
    afi_wdata_valid <= 4'b0000;

    local_rdata <= 0;
    local_rdata_valid <= 0;

    if(addr_enable)begin
      ddr2_addr <= ddr2_addr + 1'b1;
    end

    //TODO 先改32位，然后对齐时序

    if(trans_enable)begin
      trans_status <= trans_status + 1'b1;
      local_rdata_valid <= !ddr2_write;
      case(trans_status)
      0: begin
        local_rdata0 <= dio_rdata_2xa;
        local_rdata <= dio_rdata_2xa[31:0];
        //write 前序
        local_wdata0 <= local_wdata;//有延迟，要提前2周期  address count start flg
      end
      1: begin
        local_rdata1 <= dio_rdata_2xa;
        local_rdata <= local_rdata0[63:32];
        //write 前序
        local_wdata1 <= local_wdata;
        afi_dqs_burst <= 4'b1111;
      end
      2: begin
        local_rdata <= local_rdata1[31:0];
        //read 后续
        afi_dm <= 8'b00000000;
        afi_dqs_burst <= 4'b1111;
        local_wdata2 <= local_wdata;
        afi_wdata <= {local_wdata1, local_wdata0};
        afi_wdata_valid <= 4'b1111;
      end
      3: begin
        local_rdata <= local_rdata1[63:32];
        //read 后续
        afi_dm <= 8'b00000000;
        afi_dqs_burst <= 4'b1111;
        local_wdata3 <= local_wdata;
        afi_wdata <= {local_wdata, local_wdata2};
        afi_wdata_valid <= 4'b1111;

        trans_count <= trans_count + 1'b1;
        if(trans_count == TRANS_COUNT-1)begin
          trans_enable <= 0;
        end
      end
      endcase
    end

    if(!trans_enable)begin
      if(!ddr2_write)begin
        if(ddr2_timer == 10)begin
          trans_enable <= 1;
        end
      end else begin
        if(ddr2_timer == 3)begin
          trans_enable <= 1;
        end
      end
    end
    if(!ddr2_write)begin
      if(ddr2_timer == 11)begin
        addr_enable <= 1;
      end
    end else begin
      if(ddr2_timer == 2)begin
        addr_enable <= 1;
      end
    end


    my_do_activate <= 0;
    my_do_read <= 0;
    my_do_write <= 0;
    my_do_auto_precharge <= 0;
    case(status)
    DDR2_IDLE: begin
      ddr2_ack <= 0;
      ddr2_trans_count <= 0;
      local_address <= ddr2_addr_out;
      refresh_cntdown <= 0;
      ddr2_addr <= 0;
      ddr2_timer <= 0;
      ddr2_dly <= 0;
      trans_count <= 0;
      trans_status <= 0;
      trans_enable <= 0;
      addr_enable <= 0;
      if(refresh_req)begin
        status <= DDR2_REFRESH;
      end else if(ddr2_req_buff)begin
        status <= DDR2_ACTIVE;
      end
    end
    DDR2_ACTIVE: begin
      coladdr <= {local_address[CFG_MEM_IF_COL_WIDTH - 1 - 1 : 0], 1'b0};
      my_do_activate <= 1;
      status <= DDR2_ACTIVE_WAIT;
    end
    DDR2_ACTIVE_WAIT: begin
      status <= DDR2_A;
    end
    DDR2_A: begin
      my_do_read <= !ddr2_write;
      my_do_write <= ddr2_write;
      ddr2_trans_count <= ddr2_trans_count + 1'b1;
      status <= DDR2_B;
      if(ddr2_trans_count == TRANS_COUNT-1)begin
        my_do_auto_precharge <= 1;
        status <= DDR2_E;
      end
      ddr2_timer <= ddr2_timer + 1'b1;
    end
    DDR2_B: begin
      coladdr <= coladdr + 4;
      ddr2_timer <= ddr2_timer + 1'b1;
      status <= DDR2_C;
    end
    DDR2_C: begin
      ddr2_timer <= ddr2_timer + 1'b1;
      status <= DDR2_D;
    end
    DDR2_D: begin
      ddr2_timer <= ddr2_timer + 1'b1;
      status <= DDR2_A;
    end

    DDR2_E: begin
      ddr2_timer <= ddr2_timer + 1'b1;
      if(trans_enable)begin
        status <= DDR2_F;
      end
    end

    DDR2_F: begin
      if(!trans_enable)begin
        status <= DDR2_G;
      end
    end

    DDR2_G: begin
      ddr2_dly <= ddr2_dly + 1'b1;
      if(!ddr2_write)begin
        if(ddr2_dly==7)begin
            status <= DDR2_FINAL;
        end
      end else begin
        if(ddr2_dly==7)begin
            status <= DDR2_FINAL;
        end
      end
    end

    //--------------------------------------------------------------------
    DDR2_REFRESH: begin
      refresh_cntdown <= refresh_cntdown + 1'b1;
      if(refresh_cntdown_finish1)begin
        do_refresh <= 1;
      end
      if(refresh_cntdown_finish2)begin
        refresh_ack <= 1;
        status <= DDR2_IDLE;
      end
    end

    DDR2_FINAL: begin
      ddr2_ack <= 1;
      if(!ddr2_req_buff)begin
        status <= DDR2_IDLE;
      end
    end


    endcase


    // 信号 放在主状态机，数�?用延迟寄存器 + �?立状态机 请求信号+�?复位
    // 延时退�?
  end
end


wire [127:0] readValue;


debugger_usb3 #(.TRANS_COUNT(TRANS_COUNT), .TRANS_ADDR_WIDTH(TRANS_ADDR_WIDTH)) debugger_usb3_inst(
    .clk(clk_50M),
    .clk_50M(clk_50M),
    .reset_n(sys_rst_n),// && USB3_RST_OUT

    .USB3_UART_IN    (USB3_UART_IN    ),
    .USB3_RST_OUT    (USB3_RST_OUT    ),
    .USB3_PCLK       (USB3_PCLK       ),
    .USB3_DQ         (USB3_DQ         ),
    .USB3_A          (USB3_A          ),
    .USB3_SLCS_N     (USB3_SLCS_N     ),
    .USB3_SLWR_N     (USB3_SLWR_N     ),
    .USB3_SLOE_N     (USB3_SLOE_N     ),
    .USB3_SLRD_N     (USB3_SLRD_N     ),
    .USB3_PKTEND_N   (USB3_PKTEND_N   ),
    .USB3_FLAGA      (USB3_FLAGA      ),
    .USB3_FLAGB      (USB3_FLAGB      ),
    .USB3_FLAGC      (USB3_FLAGC      ),
    .USB3_FLAGD      (USB3_FLAGD      ),
    .USB3_CMD_CLK    (USB3_CMD_CLK    ),
    .USB3_CMD_DAT_U2F(USB3_CMD_DAT_U2F),
    .USB3_CMD_DAT_F2U(USB3_CMD_DAT_F2U),


    .ddr2_req(ddr2_req),
    .ddr2_write(ddr2_write),
    .ddr2_ack(ddr2_ack),

    .ddr2_addr_out(ddr2_addr_out),
    .debug_address_out(debug_address_out),
    .readValue(readValue),
    .flg(debug_flg),

    .resetIndex(resetIndex),
    .recorderIndex(recorderIndex),

    .ddr2_clk (ddr2_clk),
    .ddr2_addr (ddr2_addr),// 11:3, 2:0
    .local_rdata (local_rdata),//local_rdata  dio_rdata_2xa
    .local_rdata_valid (local_rdata_valid),
    .local_wdata (local_wdata),
    
    .dummy(dummy)
);



endmodule
